1. Field of the Invention
The present invention relates to an oscillating circuit obtaining an oscillation signal in which a second harmonic wave is suppressed.
2. Description of the Related Art
An oscillating circuit according to the related art includes a control terminal C, an output terminal P, a resonance circuit 1 whose resonance frequency varies depending on a control voltage VC that is to be applied to the control terminal C, an oscillation stage 2 whose oscillation frequency is determined on the basis of the resonance frequency of the resonance circuit 1, a buffer stage 3 which amplifies a signal output from the oscillator stage 2 and prevents variation of the oscillation frequency due to load variation, and an output matching stage 4 which matches a subsequent stage circuit to be connected to the output terminal P and suppresses harmonic waves, as shown in FIG. 5.
The resonance circuit 1 includes a coupling capacitor C1, a variable-capacitance diode VD, a resonance inductor L1, and a resonance capacitor C2. The control voltage VC applied to the control terminal C is applied to the variable-capacitance diode VD through a choke coil L2. The control terminal C is grounded in a high-frequency manner by means of a high-frequency bypass capacitor C3.
The oscillation stage 2 includes an oscillating transistor Q1, bias resistors R1 to R3, colpitts capacitors C4 and C5, a high-frequency bypass capacitor C6, a strip line SL connected in series with the bypass resistor R3, and a chip capacitor Cc connected in parallel to the strip line SL. The oscillation stage 2 is connected to the resonance circuit 1 through a coupling capacitor C7. Further, the bias resistor R3 regulates the DC bias of an emitter of the oscillating transistor Q1 serving as a current outputting terminal.
The buffer stage 3 includes a buffer transistor Q2 and bias resistors R4 and R5. The buffer stage 3 is connected to the oscillation stage 2 via a coupling capacitor C8. The output matching stage 4 includes a choke coil L3, a coupling capacitor C10, a high-frequency bypass capacitor C11, and an output terminal P. A driving power supply terminal B is grounded by a high-frequency bypass capacitor C12 (for example, refer to JP-A-08-148933).
The oscillating circuit according to the related art is configured so as to suppress harmonic waves by means of the output matching stage 4. However, when the levels of the harmonic waves included in the oscillation signal output from the emitter of the oscillating transistor Q1 are high, it is difficult to suppress the harmonic waves.